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| ltc2440 1 2440fd 2440 ta01 2440 ta01 reference voltage 0.1v to v cc analog input C0.5v ref to 0.5v ref 3-wire spi interface 6.9hz, 200nv noise, 50/60hz rejection 880hz output rate, 2v noise 10-speed serial programmable v cc 4.5v to 5.5v 4 v cc busy f o ref + sck in + in C sdo gnd cs ext sdi ltc2440 ref C typical application features applications description 24-bit high speed differential ? adc with selectable speed/resolution the ltc ? 2440 is a high speed 24-bit no latency ? tm adc with 5ppm inl and 5v offset. it uses proprietary delta-sigma architecture enabling variable speed and reso- lution with no latency. ten speed/resolution combinations (6.9hz/200nv rms to 3.5khz/25v rms ) are programmed through a simple serial interface. alternatively, by tying a single pin high or low, a fast (880hz/2v rms ) or ultralow noise (6.9hz, 200nv rms , 50/60hz rejection) speed/reso- lution combination can be easily selected. the accuracy (offset, full-scale, linearity, drift) and power dissipation are independent of the speed selected. since there is no latency, a speed/resolution change may be made between conversions with no degradation in performance. following each conversion cycle, the ltc2440 automati- cally enters a low power sleep state. power dissipation may be reduced by increasing the duration of this sleep state. for example, running at the 3.5khz conversion speed but reading data at a 100hz rate draws 240a average current (1.1mw) while reading data at a 7hz output rate draws only 25a (125w).the ltc2440 communicates through a ? exible 3-wire or 4-wire digital interface that is compatible with the ltc2410 and is available in a narrow 16-lead ssop package. simple 24-bit 2-speed acquisition system n up to 3.5khz output rate n selectable speed/resolution n 2v rms noise at 880hz output rate n 200nv rms noise at 6.9hz output rate with simultaneous 50/60hz rejection n 0.0005% inl, no missing codes n autosleep enables 20a operation at 6.9hz n <5v offset (4.5v < v cc < 5.5v, C40c to 85c) n differential input and differential reference with gnd to v cc common mode range n no latency, each conversion is accurate even after an input step n internal oscillatorno external components n pin compatible with the ltc2410 n 24-bit adc in narrow 16-lead ssop package n high speed multiplexing n weight scales n auto ranging 6-digit dvms n direct temperature measurement n high speed data acquisition speed vs rms noise , lt, ltc and ltm are registered trademarks of linear technology corporation. no latency ? is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. conversion rate (hz) 1 0.1 rms noise (v) 1 10 100 10 100 2440 ta02 1000 10000 v cc = 5v v ref = 5v v in + = v in C = 0v 2v at 880hz 200nv at 6.9hz (50/60hz rejection)
ltc2440 2 2440fd pin configuration absolute maximum ratings supply voltage (v cc ) to gnd ....................... C0.3v to 6v analog input pins voltage to gnd ...................................... C0.3v to (v cc + 0.3v) reference input pins voltage to gnd ...................................... C0.3v to (v cc + 0.3v) digital input voltage to gnd ......... C0.3v to (v cc + 0.3v) digital output voltage to gnd ....... C0.3v to (v cc + 0.3v) operating temperature range ltc2440c ............................................... 0c to 70c ltc2440i ............................................. C40c to 85c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) .................. 300c (notes 1,2) top view gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 gnd v cc ref + ref in + in sdi gnd gnd busy f o sck sdo cs ext gnd t jmax = 125c, ja = 110c/w order information lead free finish tape and reel part marking package description temperature range ltc2440cgn#pbf ltc2440cgn#trpbf 2440 narrow 16-lead ssop 0c to 70c ltc2440ign#pbf ltc2440ign#trpbf 2440i narrow 16-lead ssop C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ electrical characteristics parameter conditions min typ max units resolution (no missing codes) 0.1v v ref v cc , C0.5 ? v ref v in 0.5 ? v ref , (note 5) l 24 bits integral nonlinearity v cc = 5v, ref + = 5v, ref C = gnd, v incm = 2.5v, (note 6) ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) l 5 3 15 ppm of v ref ppm of v ref offset error 2.5v ref + v cc , ref C = gnd, gnd in + = in C v cc (note 12) l 2.5 5 v offset error drift 2.5v ref + v cc , ref C = gnd, gnd in + = in C v cc 20 nv/ c positive full-scale error ref + = 5v, ref C = gnd, in + = 3.75v, in C = 1.25v ref + = 2.5v, ref C = gnd, in + = 1.875v, in C = 0.625v l l 10 10 30 50 ppm of v ref ppm of v ref positive full-scale error drift 2.5v ref + v cc , ref C = gnd, in + = 0.75ref + , in C = 0.25 ? ref + 0.2 ppm of v ref /c negative full-scale error ref + = 5v, ref C = gnd, in + = 1.25v, in C = 3.75v ref + = 2.5v, ref C = gnd, in + = 0.625v, in C = 1.875v l l 10 10 30 50 ppm of v ref ppm of v ref negative full-scale error drift 2.5v ref + v cc , ref C = gnd, in + = 0.25 ? ref + , in C = 0.75 ? ref + 0.2 ppm of v ref /c total unadjusted error 5v v cc 5.5v, ref + = 2.5v, ref C = gnd, v incm = 1.25v 5v v cc 5.5v, ref + = 5v, ref C = gnd, v incm = 2.5v ref + = 2.5v, ref C = gnd, v incm = 1.25v, (note 6) 15 15 15 ppm of v ref ppm of v ref ppm of v ref input common mode rejection dc 2.5v ref + v cc , ref C = gnd, gnd in C = in + v cc 120 db the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (notes 3, 4) ltc2440 3 2440fd analog input and reference symbol parameter conditions min typ max units in + absolute/common mode in + voltage l gnd C 0.3v v cc + 0.3v v in C absolute/common mode in C voltage l gnd C 0.3v v cc + 0.3v v v in input differential voltage range (in + C in C ) l Cv ref /2 v ref /2 v ref + absolute/common mode ref + voltage l 0.1 v cc v ref C absolute/common mode ref C voltage l gnd v cc C 0.1v v v ref reference differential voltage range (ref + C ref C ) l 0.1 v cc v c s(in + ) in + sampling capacitance 3.5 pf c s(in C ) in C sampling capacitance 3.5 pf c s(ref + ) ref + sampling capacitance 3.5 pf c s(ref C ) ref C sampling capacitance 3.5 pf i dc_leak(in + , in C , ref + , ref C ) leakage current, inputs and reference cs = v cc , in + = gnd, in C = gnd, ref + = 5v, ref C = gnd l C100 10 100 na i sample(in + , in C , ref + , ref C ) average input/reference current during sampling varies, see applications section the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) digital inputs and digital outputs symbol parameter conditions min typ max units v in high level input voltage cs, f o , sdi 4.5v v cc 5.5v l 2.5 v v il low level input voltage cs, f o , sdi 4.5v v cc 5.5v l 0.8 v v in high level input voltage sck 4.5v v cc 5.5v (note 8) l 2.5 v v il low level input voltage sck 4.5v v cc 5.5v (note 8) l 0.8 v i in digital input current cs, f o 0v v in v cc l C10 10 a i in digital input current sck 0v v in v cc (note 8) l C10 10 a c in digital input capacitance cs, f o 10 pf c in digital input capacitance sck (note 8) 10 pf v oh high level output voltage sdo, busy i o = C800a l v cc C 0.5v v v ol low level output voltage sdo, busy i o = 1.6ma l 0.4v v v oh high level output voltage sck i o = C800a (note 9) l v cc C 0.5v v v ol low level output voltage sck i o = 1.6ma (note 9) l 0.4v v i oz hi-z output leakage sdo l C10 10 a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) ltc2440 4 2440fd power requirements note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: v cc = 4.5 to 5.5v unless otherwise speci? ed. v ref = ref + C ref C , v refcm = (ref + + ref C )/2; v in = in + C in C , v incm = (in + + in C )/2. note 4: f o pin tied to gnd or to external conversion clock source with f eosc = 10mhz unless otherwise speci? ed. note 5: guaranteed by design, not subject to test. note 6: integral nonlinearity is de? ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. symbol parameter conditions min typ max units v cc supply voltage l 4.5 5.5 v i cc supply current conversion mode sleep mode cs = 0v (note 7) cs = v cc (note 7) l l 8 8 11 30 ma a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) timing characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 3) note 7: the converter uses the internal oscillator. note 8: the converter is in external sck mode of operation such that the sck pin is used as a digital input. the frequency of the clock signal driving sck during the data output is f esck and is expressed in hz. note 9: the converter is in internal sck mode of operation such that the sck pin is used as a digital output. in this mode of operation, the sck pin has a total equivalent load capacitance of c load = 20pf. note 10: the external oscillator is connected to the f o pin. the external oscillator frequency, f eosc , is expressed in khz. note 11: the converter uses the internal oscillator. f o = 0v. note 12: guaranteed by design and test correlation. note 13: there is an internal reset that adds an additional 1s (typical) to the conversion time. symbol parameter conditions min typ max units f eosc external oscillator frequency range l 0.1 20 mhz t heo external oscillator high period l 25 10000 ns t leo external oscillator low period l 25 10000 ns t conv conversion time osr = 256 (sdi = 0) osr = 32768 (sdi = 1) external oscillator (note 10, 13) l l l 0.99 126 1.13 145 40 ? osr + 170 f eosc (khz) 1.33 170 ms ms ms f isck internal sck frequency internal oscillator (note 9) external oscillator (notes 9, 10) l 0.8 0.9 f eosc /10 1 d isck internal sck duty cycle (note 9) l 45 55 % f esck external sck frequency range (note 8) l 20 mhz t lesck external sck low period (note 8) l 25 ns t hesck external sck high period (note 8) l 25 ns t dout_isck internal sck 32-bit data output time internal oscillator (notes 9, 11) external oscillator (notes 9, 10) l 30.9 35.3 320/f eosc 41.6 s s t dout_esck external sck 32-bit data output time (note 8) l 32/f esck s t 1 cs to sdo low z (note 12) l 02 5 n s t 2 cs to sdo high z (note 12) l 02 5 n s t 3 cs to sck (note 9) l 5 s t 4 cs to sck (notes 8, 12) l 25 ns t kqmax sck to sdo valid l 25 ns t kqmin sdo hold after sck (note 5) l 15 ns t 5 sck set-up before cs l 50 ns t 7 sdi setup before sck (note 5) l 10 ns t 8 sdi hold after sck (note 5) l 10 ns ltc2440 5 2440fd typical performance characteristics integral nonlinearity f out = 3.5khz integral nonlinearity f out = 1.76khz integral nonlinearity f out = 880hz integral nonlinearity f out = 440hz integral nonlinearity f out = 220hz integral nonlinearity f out = 110hz integral nonlinearity f out = 55hz integral nonlinearity f out = 27.5hz integral nonlinearity f out = 13.75hz v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g01 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g02 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g03 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g04 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g05 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g06 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g07 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g08 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g09 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c ltc2440 6 2440fd typical performance characteristics integral nonlinearity f out = 6.875hz integral nonlinearity vs conversion rate integral nonlinearity vs v incm integral nonlinearity vs temperature integral nonlinearity vs temperature C full-scale error vs v ref + full-scale error vs v ref C full-scale error vs v cc +full-scale error vs v cc v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g10 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v f o = gnd t a = 25c conversion rate (hz) 0 0 inl error (ppm of v ref ) 2.5 5.0 7.5 10.0 500 1000 1500 2000 2440 g11 2500 3000 3500 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd C2.5v v in 2.5v v incm = 2.5v f o = gnd t a = 25c v in (v) C1.25 inl error (ppm of v ref ) 0 5 0.75 2440 g12 C5 C10 C0.75 C0.25 1.25 10 0.25 v cc = 5v v ref = 2.5v v ref + = 2.5v v ref C = gnd osr = 32768 f o = gnd t a = 25c v incm = 1.25v v incm = 3.75v v incm = 2.5v v in (v) C1.25 inl error (ppm of v ref ) 0 5 0.75 2440 g13 C5 C10 C0.75 C0.25 1.25 10 0.25 v cc = 5v v ref = 2.5v v ref + = 2.5v v ref C = gnd v incm = 1.25v osr = 32768 f o = gnd t a = 25c t a = C55c t a = 125c v in (v) C2.5 inl error (ppm of v ref ) 0 5 1.5 2440 g14 C5 C10 C1.5 C0.5 0 2.5 10 0.5 C2 C1 2 1 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v osr = 32768 f o = gnd t a = C25c t a = 125c t a = 25c v ref (v) 0 Cfull-scale error (ppm of v ref ) 0 10 4 2440 g15 C10 C20 1 2 3 5 20 v ref (v) 0 +full-scale error (ppm of v ref ) 0 10 4 2440 g16 C10 C20 1 2 3 5 20 v cc (v) 4.5 full-scale error (ppm of v ref ) 6 8 10 5.3 2440 g17 4 2 5 7 9 3 1 0 4.7 4.9 5.1 5.5 v ref = 2.5v v ref + = 2.5v v ref C = gnd v incm = 1.25v osr = 32768 f o = gnd t a = 25c v cc (v) 4.5 full-scale error (ppm of v ref ) C4 C2 0 5.3 2440 g18 C6 C8 C5 C3 C1 C7 C9 C10 4.7 4.9 5.1 5.5 v ref = 2.5v v ref + = 2.5v v ref C = gnd v incm = 1.25v osr = 32768 f o = gnd t a = 25c ltc2440 7 2440fd typical performance characteristics negative full-scale error vs temperature positive full-scale error vs temperature offset error vs v cc offset error vs conversion rate offset error vs v incm rms noise vs temperature offset error vs temperature inl vs output rate (osr = 128) external clock sweep 10mhz to 20mhz rms noise vs output rate (osr = 128) external clock sweep 10mhz to 20mhz temperature (c) C55 full-scale error (ppm of v ref ) 5 10 15 125 2440 g19 C5 C20 C25 5 35 65 95 20 0 C10 C15 4.5v 5v 5.5v v cc = 4.5v v ref = 4.5v v ref + = 4.5v v ref C = gnd v incm = 2.25v osr = 32768 f o = gnd v cc = 5.5v, 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v osr = 32768 f o = gnd temperature (c) C55 full-scale error (ppm of v ref ) 5 10 15 125 2440 g20 C5 C20 C25 5 35 65 95 20 0 C10 C15 4.5v 5v 5.5v v cc = 4.5v v ref = 4.5v v ref + = 4.5v v ref C = gnd v incm = 2.25v osr = 32768 f o = gnd v cc = 5.5v, 5v v ref = 5v v ref + = 5v v ref C = gnd v incm = 2.5v osr = 32768 f o = gnd v cc (v) 4.5 offset error (ppm of v ref ) 0 2.5 5.3 2440 g21 C2.5 C5.0 4.7 4.9 5.1 5.5 5.0 v ref = 2.5v v ref + = 2.5v v ref C = gnd v in + = v in C = gnd osr = 32768 f o = gnd t a = 25c conversion rate (hz) 0 C5.0 offset error (ppm of v ref ) C2.5 0 2.5 5.0 500 1000 1500 2000 2440 g22 2500 3000 3500 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v in + = v in C = gnd f o = gnd t a = 25c v incm (v) 0 offset error (ppm of v ref ) 0 2.5 4 2440 g23 C2.5 C5.0 1 2 3 5 5.0 v cc = 5v v ref = 5v v ref + = 5v v ref C = gnd v in + = v in C = v incm osr = 32768 f o = gnd t a = 25c temperature (c) C55 0.5 rms noise (v) 1.0 1.5 2.0 2.5 3.5 C25 53565 2440 g24 95 125 3.0 v cc = 4.5v v ref = 2.5v v ref + = 2.5v v ref C = gnd v in + = v in C = gnd osr = 256 f o = gnd v cc = 5.5v, 5v v ref = 5v v ref + = 5v v ref C = gnd v in + = v in C = gnd osr = 256 f o = gnd v cc = 5v v cc = 5.5v v cc = 4.5v temperature (c) C55 C5.0 offset error (v) C2.5 0 2.5 5.0 C25 53565 2440 g25 95 125 v cc = 4.5v v ref = 2.5v v ref + = 2.5v v ref C = gnd v in + = v in C = gnd osr = 256 f o = gnd v cc = 5.5v, 5v v ref = 5v v ref + = 5v v ref C = gnd v in + = v in C = gnd osr = 256 f o = gnd v cc = 5v v cc = 5.5v v cc = 4.5v output rate (hz) 2000 2500 3000 3500 4000 linearity (bits) 2440 g26 20 18 16 14 12 10 8 6 4 2 0 external clock 10mhz (or internal oscillator) v ref = v cc = 5v temp = 25c sweep (v in C v ref /2) to v ref /2 external clock 20mhz output rate (hz) 2000 2500 3000 3500 4000 rms noise (v) 2440 g27 5 4 3 2 1 0 v ref = v cc = 5v temp = 25c v in v ref /2 ltc2440 8 2440fd pin functions gnd (pins 1, 8, 9, 16): ground. multiple ground pins internally connected for optimum ground current ? ow and v cc decoupling. connect each one of these pins to a ground plane through a low impedance connection. all four pins must be connected to ground for proper operation. v cc (pin 2): positive supply voltage. bypass to gnd (pin 1) with a 10f tantalum capacitor in parallel with 0.1f ceramic capacitor as close to the part as possible. ref + (pin 3), ref C (pin 4): differential reference input. the voltage on these pins can have any value between gnd and v cc as long as the reference positive input, ref + , is maintained more positive than the reference negative input, ref C , by at least 0.1v. in + (pin 5), in C (pin 6): differential analog input. the voltage on these pins can have any value between gnd C 0.3v and v cc + 0.3v. within these limits the converter bipolar input range (v in = in + C in C ) extends from C0.5 ? (v ref ) to 0.5 ? (v ref ). outside this input range the converter produces unique overrange and underrange output codes. sdi (pin 7): serial data input. this pin is used to select the speed/resolution of the converter. if sdi is grounded (pin compatible with ltc2410) the device outputs data at 880hz with 21 bits effective resolution. by tying sdi high, the converter enters the ultralow noise mode (200nv rms ) with simultaneous 50/60hz rejection at 6.9hz output rate. sdi may be driven logic high or low anytime dur- ing the conversion or sleep state in order to change the speed/resolution. the conversion immediately following the data output cycle will be valid and performed at the newly selected output rate/resolution. sdi may also be programmed by a serial input data stream under control of sck during the data output cycle. one of ten speed/resolu- tion ranges (from 6.9hz/200nv rms to 3.5khz/21v rms ) may be selected. the ? rst conversion following a new selection is valid and performed at the newly selected speed/resolution. ext (pin 10): internal/external sck selection pin. this pin is used to select internal or external sck for outputting data. if ext is tied low (pin compatible with the ltc2410), the device is in the external sck mode and data is shifted out the device under the control of a user applied serial clock. if ext is tied high, the internal serial clock mode is selected. the device generates its own sck signal and outputs this on the sck pin. a framing signal busy (pin 15) goes low indicating data is being output. cs (pin 11): active low digital input. a low on this pin enables the sdo digital output and wakes up the adc. following each conversion the adc automatically enters the sleep mode and remains in this low power state as long as cs is high. a low-to-high transition on cs during the data output transfer aborts the data transfer and starts a new conversion. sdo (pin 12): three-state digital output. during the data output period, this pin is used as serial data output. when the chip select cs is high (cs = v cc ) the sdo pin is in a high impedance state. during the conversion and sleep periods, this pin is used as the conversion status output. the conversion status can be observed by pulling cs low. sck (pin 13): bidirectional digital clock pin. in internal serial clock operation mode, sck is used as digital output for the internal serial interface clock during the data output period. in external serial clock operation mode, sck is used as digital input for the external serial interface clock during the data output period. the serial clock operation mode is determined by the logic level applied to the ext pin. f o (pin 14): frequency control pin. digital input that con- trols the internal conversion clock. when f o is connected to v cc or gnd, the converter uses its internal oscillator running at 9mhz. the conversion rate is determined by the selected osr such that t conv (in ms) = (40 ? osr + 170)/9000 (t conv = 1.137ms at osr = 256, t conv = 146ms at osr = 32768). the ? rst null is located at 8/ t conv , 7khz at osr = 256 and 55hz (simultaneous 50/60hz) at osr = 32768. when f o is driven by an oscillator with frequency f eosc (in khz), the conversion time becomes t conv = (40 ? osr + 170)/f eosc (in ms) and the ? rst null remains 8/ t conv . busy (pin 15): conversion in progress indicator. for compatibility with the ltc2410, this pin should not be tied to ground. this pin is high while the conversion is in progress and goes low indicating the conversion is complete and data is ready. it remains low during the sleep and data output states. at the conclusion of the data output state, it goes high indicating a new conversion has begun. ltc2440 9 2440fd functional block diagram test circuits applications information figure 1. functional block diagram figure 2. ltc2440 state transition diagram converter operation converter operation cycle the ltc2440 is a high speed, delta-sigma analog-to-digital converter with an easy to use 4-wire serial interface (see figure 1). its operation is made up of three states. the converter operating cycle begins with the conversion, followed by the low power sleep state and ends with the data output (see figure 2). the 4-wire interface consists of serial data input (sdi), serial data output (sdo), serial clock (sck) and chip select (cs ). the interface, timing, operation cycle and data out format is compatible with the ltc2410. autocalibration and control dac decimating fir internal oscillator serial interface adc gnd v cc in + in C sdo sck ref + ref C cs sdi busy ext f o (int/ext) 2440 f01 C+ + C 1.69k sdo 2440 ta03 hi-z to v oh v ol to v oh v oh to hi-z c load = 20pf 1.69k sdo 2440 ta04 hi-z to v ol v oh to v ol v ol to hi-z c load = 20pf v cc convert sleep data output 2440 f02 true false cs = low and sck ltc2440 10 2440fd applications information initially, the ltc2440 performs a conversion. once the conversion is complete, the device enters the sleep state. while in this sleep state, power consumption is reduced below 10a. the part remains in the sleep state as long as cs is high. the conversion result is held inde? nitely in a static shift register while the converter is in the sleep state. once cs is pulled low, the device begins outputting the conversion result. there is no latency in the conversion result. the data output corresponds to the conversion just performed. this result is shifted out on the serial data out pin (sdo) under the control of the serial clock (sck). data is updated on the falling edge of sck allowing the user to reliably latch data on the rising edge of sck (see figure 3). the data output state is concluded once 32-bits are read out of the adc or when cs is brought high. the device automatically initiates a new conversion and the cycle repeats. through timing control of the cs, sck and ext pins, the ltc2440 offers several ? exible modes of operation (internal or external sck). these various modes do not require programming con? guration registers; moreover, they do not disturb the cyclic operation described above. these modes of operation are described in detail in the serial interface timing modes section. ease of use the ltc2440 data output has no latency, ? lter settling delay or redundant data associated with the conversion cycle. there is a one-to-one correspondence between the conversion and the output data. therefore, multiplexing multiple analog voltages is easy. speed/resolution adjust- ments may be made seamlessly between two conversions without settling errors. the ltc2440 performs offset and full-scale calibrations every conversion cycle. this calibration is transparent to the user and has no effect on the cyclic operation described above. the advantage of continuous calibration is extreme stability of offset and full-scale readings with respect to time, supply voltage change and temperature drift. power-up sequence the ltc2440 automatically enters an internal reset state when the power supply voltage v cc drops below ap- proximately 2.2v. this feature guarantees the integrity of the conversion result and of the serial interface mode selection. when the v cc voltage rises above this critical threshold, the converter creates an internal power-on-reset (por) signal with a duration of approximately 0.5ms. the por signal clears all internal registers. following the por signal, the ltc2440 starts a normal conversion cycle and follows the succession of states described above. the ? rst conversion result following por is accurate within the speci? cations of the device if the power supply voltage is restored within the operating range (4.5v to 5.5v) before the end of the por time interval. reference voltage range this converter accepts a truly differential external reference voltage. the absolute/common mode voltage speci? cation for the ref + and ref C pins covers the entire range from gnd to v cc . for correct converter operation, the ref + pin must always be more positive than the ref C pin. the ltc2440 can accept a differential reference voltage from 0.1v to v cc . the converter output noise is determined by the thermal noise of the front-end circuits, and as such, its value in microvolts is nearly constant with reference voltage. a decrease in reference voltage will not signi? - cantly improve the converters effective resolution. on the other hand, a reduced reference voltage will improve the converters overall inl performance. input voltage range the analog input is truly differential with an absolute/com- mon mode range for the in + and in C input pins extending from gnd C 0.3v to v cc + 0.3v. outside these limits, the esd protection devices begin to turn on and the errors due to input leakage current increase rapidly. within these limits, the ltc2440 converts the bipolar differential input signal, v in = in + C in C , from Cfs = C0.5 ? v ref to +fs = ltc2440 11 2440fd applications information figure 3. output data timing 0.5 ? v ref where v ref = ref + C ref C . outside this range, the converter indicates the overrange or the underrange condition using distinct output codes. output data format the ltc2440 serial output data stream is 32-bits long. the ? rst 3-bits represent status information indicating the sign and conversion state. the next 24-bits are the conversion result, msb ? rst. the remaining 5-bits are sub lsbs beyond the 24-bit level that may be included in averaging or discarded without loss of resolution. in the case of ultrahigh resolution modes, more than 24 effec- tive bits of performance are possible (see table 3). under these conditions, sub lsbs are included in the conversion result and represent useful information beyond the 24-bit level. the third and fourth bit together are also used to indicate an underrange condition (the differential input voltage is below Cfs) or an overrange condition (the dif- ferential input voltage is above +fs). for input conditions in excess of twice full scale (|v in | v ref ), the converter may indicate either overrange or underrange. once the input returns to the normal operating range, the conversion result is immediately accurate within the speci? cations of the device. bit 31 (? rst output bit) is the end of conversion ( eoc) indicator. this bit is available at the sdo pin during the conversion and sleep states whenever the cs pin is low. this bit is high during the conversion and goes low when the conversion is complete. bit 30 (second output bit) is a dummy bit (dmy) and is always low. bit 29 (third output bit) is the conversion result sign indicator (sig). if v in is >0, this bit is high. if v in is <0, this bit is low. bit 28 (fourth output bit) is the most signi? cant bit (msb) of the result. this bit in conjunction with bit 29 also provides the underrange or overrange indication. if both bit 29 and bit 28 are high, the differential input voltage is above +fs. if both bit 29 and bit 28 are low, the differential input voltage is below Cfs. the function of these bits is summarized in table 1. table 1. ltc2440 status bits input range bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb v in 0.5 ? v ref 0011 0v v in < 0.5 ? v ref 0010 C0.5 ? v ref v in < 0v 0001 v in < C0.5 ? v ref 0000 bits ranging from 28 to 5 are the 24-bit conversion result msb ? rst. bit 5 is the least signi? cant bit (lsb). bits ranging from 4 to 0 are sub lsbs below the 24-bit level. bits 4 to bit 0 may be included in averaging or dis- carded without loss of resolution. data is shifted out of the sdo pin under control of the serial clock (sck), see figure 3. whenever cs is high, sdo remains high impedance. in order to shift the conversion result out of the device, cs must ? rst be driven low. eoc is seen at the sdo pin of the device once cs is pulled low. eoc changes real time from high to low at the completion of a conversion. this signal may be used as an interrupt for an external msb sig 0 1 2 3 4 5 262732 bit 0 bit 27 bit 5 lsb 24 bit 28 bit 29 bit 30 sdo sck busy cs eoc bit 31 sleep data output conversion 2440 f03 hi-z ltc2440 12 2440fd applications information microcontroller. bit 31 ( eoc) can be captured on the ? rst rising edge of sck. bit 30 is shifted out of the device on the ? rst falling edge of sck. the ? nal data bit (bit 0) is shifted out on the falling edge of the 31st sck and may be latched on the rising edge of the 32nd sck pulse. on the falling edge of the 32nd sck pulse, sdo goes high indicating the initiation of a new conversion cycle. this bit serves as eoc (bit 31) for the next conversion cycle. table 2 summarizes the output data format. as long as the voltage on the in + and in C pins is main- tained within the C0.3v to (v cc + 0.3v) absolute maximum operating range, a conversion result is generated for any differential input voltage v in from Cfs = C0.5 ? v ref to +fs = 0.5 ? v ref . for differential input voltages greater than +fs, the conversion result is clamped to the value corresponding to the +fs + 1lsb. for differential input voltages below Cfs, the conversion result is clamped to the value corresponding to Cfs C 1lsb. serial interface pins the ltc2440 transmits the conversion results and receives the start of conversion command through a synchronous 2-wire, 3-wire or 4-wire interface. during the conversion and sleep states, this interface can be used to assess the converter status and during the data output state it is used to read the conversion result and program the speed/resolution. serial clock input/output (sck) the serial clock signal present on sck (pin 13) is used to synchronize the data transfer. each bit of data is shifted out the sdo pin on the falling edge of the serial clock. in the internal sck mode of operation, the sck pin is an output and the ltc2440 creates its own serial clock. in the external sck mode of operation, the sck pin is used as input. the internal or external sck mode is selected by tying ext (pin 10) low for external sck and high for internal sck. serial data output (sdo) the serial data output pin, sdo (pin 12), provides the result of the last conversion as a serial bit stream (msb ? rst) during the data output state. in addition, the sdo pin is used as an end of conversion indicator during the conversion and sleep states. when cs (pin 11) is high, the sdo driver is switched to a high impedance state. this allows sharing the serial interface with other devices. if cs is low during the convert or sleep state, sdo will output eoc. if cs is low during the conversion phase, the eoc bit appears high on the sdo pin. once the conversion is complete, eoc goes low. the device remains in the sleep state until the ? rst rising edge of sck occurs while cs = low. table 2. ltc2440 output data format differential input voltage v in * bit 31 eoc bit 30 dmy bit 29 sig bit 28 msb bit 27 bit 26 bit 25 bit 0 v in * 0.5 ? v ref ** 00110000 0.5 ? v ref ** C 1lsb 0 0 1 0 1 1 1 1 0.25 ? v ref ** 00101000 0.25 ? v ref ** C 1lsb 0 0 1 0 0 1 1 1 0 00100000 C1lsb 00011111 C0.25 ? v ref ** 00011000 C0.25 ? v ref ** C 1lsb 0 0 0 1 0 1 1 1 C0.5 ? v ref ** 00010000 v in * < C0.5 ? v ref ** 00001111 *the differential input voltage v in = in + C in C . **the differential reference voltage v ref = ref + C ref C . ltc2440 13 2440fd applications information chip select input (cs) the active low chip select, cs (pin 11), is used to test the conversion status and to enable the data output transfer as described in the previous sections. in addition, the cs signal can be used to trigger a new con- version cycle before the entire serial data transfer has been completed. the ltc2440 will abort any serial data transfer in progress and start a new conversion cycle anytime a low-to-high transition is detected at the cs pin after the converter has entered the data output state (i.e., after the ? fth falling edge of sck occurs with cs = low). serial data input (sdi)logic level speed selection the serial data input (sdi, pin 7) is used to select the speed/resolution of the ltc2440. a simple 2-speed control is selectable by either driving sdi high or low. if sdi is grounded (pin compatible with ltc2410) the device outputs data at 880hz with 21 bits effective resolution. by tying sdi high, the converter enters the ultralow noise mode (200nv rms ) with simultaneous 50/60hz rejection at 6.9hz output rate. sdi may be driven logic high or low anytime during the conversion or sleep state in order to change the speed/resolution. the conversion immediately following the data output cycle will be valid and performed at the newly selected output rate/resolution. changing sdi logic state during the data output cycle should be avoided as speed resolution other than 6.9hz or 880hz may be selected. for example, if sdi is changed from logic 0 to logic 1 after the second rising edge of sck, the conversion rate will change from 880hz to 55hz (the following values are listed in table 3: osr4 = 0, osr3 = 0, osr2 = 1, osr1 = 1 and osr0 = 1). if sdi remains high, the conversion rate will switch to the desired 6.9hz speed immediately following the conversion at 55hz. the 55hz rate conversion cycle will be a valid result as well as the ? rst 6.9hz result. on the other hand, if sdi is changed to a 1 anytime before the ? rst rising edge of sck, the following conversion rate will become 6.9hz. if sdi is changed to a 1 after the 5th rising edge of sck, the next conversion will remain 880hz while all subsequent conversions will be at 6.9hz. serial data input (sdi)serial input speed selection sdi may also be programmed by a serial input data stream under control of sck during the data output cycle, see figure 4. one of ten speed/resolution ranges (from 6.9hz/200nv rms to 3.5khz/21v rms ) may be selected, see table 3. the conversion following a new selection is valid and performed at the newly selected speed/resolution. busy the busy output (pin 15) is used to monitor the state of conversion, data output and sleep cycle. while the part is converting, the busy pin is high. once the conversion is complete, busy goes low indicating the conversion is complete and data out is ready. the part now enters the low power sleep state. busy remains low while data is shifted out of the device. it goes high at the conclusion of the data output cycle indicating a new conversion has begun. this rising edge may be used to ? ag the comple- tion of the data read cycle. serial interface timing modes the ltc2440s 2-wire, 3-wire or 4-wire interface is spi and microwire compatible. this interface offers several ? exible modes of operation. these include internal/external serial clock, 2-wire or 3-wire i/o, single cycle conversion and autostart. the following sections describe each of these serial interface timing modes in detail. in all these cases, the converter can use the internal oscillator (f o = low) or an external oscillator connected to the f o pin. see table 4 for a summary. external serial clock, single cycle operation (spi/microwire compatible) this timing mode uses an external serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 5. the serial clock mode is selected by the ext pin. to select the external serial clock mode, ext must be tied low. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. while cs is pulled low, eoc is output to the sdo pin. ltc2440 14 2440fd applications information figure 4. sdi speed/resolution programming msb bit 28 bit 27 bit 26 bit 25 bit 1 bit 0 lsb hi-z 2440 f04 sig bit 29 0 bit 30 eoc hi-z cs sck sdi sdo busy bit 31 *osr4 bit must be at first sck rising edge during serial data out cycle osr4* osr3 osr2 osr1 osr0 table 3. sdi speed/resolution programming osr4 osr3 osr2 osr1 osr0 conversion rate rms noise enob osr internal 9mhz clock external 10.24mhz clock x 0 0 0 1 3.52khz 4khz 23v 17 64 x 0 0 1 0 1.76khz 2khz 3.5v 20 128 0 0 0 0 0 880hz 1khz 2v 21.3 256* x 0 0 1 1 880hz 1khz 2v 21.3 256 x 0 1 0 0 440hz 500hz 1.4v 21.8 512 x 0 1 0 1 220hz 250hz 1v 22.4 1024 x 0 1 1 0 110hz 125hz 750nv 22.9 2048 x 0 1 1 1 55hz 62.5hz 510nv 23.4 4096 x 1 0 0 0 27.5hz 31.25hz 375nv 24 8192 x 1 0 0 1 13.75hz 15.625hz 250nv 24.4 16384 x 1 1 1 1 6.875hz 7.8125hz 200nv 24.6 32768** **address allows tying sdi high *additional address to allow tying sdi low table 4. ltc2440 interface timing modes con? guration sck source conversion cycle control data output control connection and waveforms external sck, single cycle conversion external cs and sck cs and sck figures 5, 6 external sck, 2-wire i/o external sck sck figure 7 internal sck, single cycle conversion internal cs cs figures 8, 9 internal sck, 2-wire i/o, continuous conversion internal continuous internal figure 10 ltc2440 15 2440fd applications information figure 5. external serial clock, single cycle operation eoc = 1 (busy = 1) while a conversion is in progress and eoc = 0 (busy = 0) if the device is in the sleep state. independent of cs, the device automatically enters the low power sleep state once the conversion is complete. when the device is in the sleep state ( eoc = 0), its con- version result is held in an internal static shift register. the device remains in the sleep state until the ? rst rising edge of sck is seen. data is shifted out the sdo pin on each falling edge of sck. this enables external circuitry to latch the output on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck and the last bit of the conversion result can be latched on the 32nd rising edge of sck. on the 32nd falling edge of sck, the device begins a new conversion. sdo goes high (eoc = 1) and busy goes high indicating a conversion is in progress. at the conclusion of the data cycle, cs may remain low and eoc monitored as an end-of-conversion interrupt. alternatively, cs may be driven high setting sdo to hi-z and busy monitored for the completion of a conversion. as described above, cs may be pulled low at any time in order to monitor the conversion status on the sdo pin. typically, cs remains low during the data output state. however, the data output state may be aborted by pulling cs high anytime between the ? fth falling edge (sdi must be properly loaded each cycle) and the 32nd falling edge of sck, see figure 6. on the rising edge of cs, the device aborts the data output state and immediately initiates a new conversion. this is useful for systems not requiring all 32-bits of output data, aborting an invalid conversion cycle or synchronizing the start of a conversion. external serial clock, 2-wire i/o this timing mode utilizes a 2-wire serial i/o interface. the conversion result is shifted out of the device by an externally generated serial clock (sck) signal, see figure 7. cs may be permanently tied to ground, simplifying the user interface or isolation barrier. the external serial clock mode is selected by tying ext low. since cs is tied low, the end-of-conversion (eoc) can be continuously monitored at the sdo pin during the convert and sleep states. conversely, busy (pin 15) may be used to monitor the status of the conversion cycle. eoc or busy may be used as an interrupt to an external eoc bit 31 sdo busy sck (external) cs test eoc sub lsb msb sig bit 0 lsb bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2440 f05 conversion hi-z hi-z hi-z test eoc test eoc = external oscillator = internal oscillator v cc f o busy ref + ref C sck in + in C sdo gnd cs ext 2 14 15 3 4 13 5 6 12 1, 8, 9, 16 11 10 sdi 7 reference voltage 0.1v to v cc analog input range C0.5v ref to 0.5v ref 1f 4.5v to 5.5v ltc2440 3-wire spi interface 200nv noise, 50/60hz rejection 10-speed/resolution programmable 2v noise, 880hz output rate v cc ltc2440 16 2440fd applications information figure 6. external serial clock, reduced data output length figure 7. external serial clock, cs = 0 operation (2-wire) sdo 15 busy sck (external) cs data output conversion sleep sleep test eoc test eoc data output hi-z hi-z hi-z conversion 2410 f06 msb sig bit 8 bit 27 bit 9 bit 28 bit 29 bit 30 eoc bit 31 bit 0 eoc hi-z test eoc = external oscillator = internal oscillator v cc f o ref + ref C sck in + in C sdo gnd cs ext 2 14 busy 15 3 4 13 5 6 12 1, 8, 9, 16 11 10 sdi 7 reference voltage 0.1v to v cc analog input range C0.5v ref to 0.5v ref 1f 4.5v to 5.5v ltc2440 3-wire spi interface 200nv noise, 50/60hz rejection 10-speed/resolution programmable 2v noise, 880hz output rate v cc eoc bit 31 sdo busy sck (external) cs msb sig bit 0 lsb 24 bit 5 bit 27 bit 26 bit 28 bit 29 bit 30 sleep data output conversion 2440 f07 conversion = external oscillator = internal oscillator v cc f o ref + ref C sck in + in C sdo gnd cs ext 2 14 busy 15 3 4 13 5 6 12 1, 8, 9, 16 11 10 sdi 7 reference voltage 0.1v to v cc analog input range C0.5v ref to 0.5v ref 1f 4.5v to 5.5v ltc2440 3-wire spi interface 200nv noise, 50/60hz rejection 10-speed/resolution programmable 2v noise, 880hz output rate v cc ltc2440 17 2440fd applications information figure 8. internal serial clock, single cycle operation controller indicating the conversion result is ready. eoc = 1 (busy = 1) while the conversion is in progress and eoc = 0 (busy = 0) once the conversion enters the low power sleep state. on the falling edge of eoc /busy, the conversion result is loaded into an internal static shift register. the device remains in the sleep state until the ? rst rising edge of sck. data is shifted out the sdo pin on each falling edge of sck enabling external circuitry to latch data on the rising edge of sck. eoc can be latched on the ? rst rising edge of sck. on the 32nd falling edge of sck, sdo and busy go high (eoc = 1) indicating a new conversion has begun. internal serial clock, single cycle operation this timing mode uses an internal serial clock to shift out the conversion result and a cs signal to monitor and control the state of the conversion cycle, see figure 8. in order to select the internal serial clock timing mode, the ext pin must be tied high. the serial data output pin (sdo) is hi-z as long as cs is high. at any time during the conversion cycle, cs may be pulled low in order to monitor the state of the converter. once cs is pulled low, sck goes low and eoc is output to the sdo pin. eoc = 1 while a conversion is in progress and eoc = 0 if the device is in the sleep state. alterna- tively, busy (pin 15) may be used to monitor the status of the conversion in progress. busy is high during the conversion and goes low at the conclusion. it remains low until the result is read from the device. when testing eoc, if the conversion is complete (eoc = 0), the device will exit the sleep state and enter the data output state if cs remains low. in order to prevent the device from exiting the low power sleep state, cs must be pulled high before the ? rst rising edge of sck. in the internal sck timing mode, sck goes high and the device begins outputting data at time t eoctest after the falling edge of cs (if eoc = 0) or t eoctest after eoc goes low (if cs is low during the falling edge of eoc). the value of t eoctest is 500ns. if cs is pulled high before time te octest , the device remains in the sleep state. the conversion result is held in the internal static shift register. if cs remains low longer than t eoctest , the ? rst rising edge of sck will occur and the conversion result is serially shifted out of the sdo pin. the data output cycle begins sdo busy sck (internal) cs msb sig bit 0 lsb 24 bit 5 test eoc bit 27 bit 26 bit 28 bit 29 bit 30 eoc bit 31 sleep data output conversion conversion 2440 f08 ltc2440 20 2440fd applications information osr, the noise performance of the device is 200nv rms with better than 80db rejection of 50hz 2% and 60hz 2%. since the osr is large (32,768) the wide band rejection is extremely large and the antialiasing requirements are simple. the ? rst multiple of f s occurs at 55hz ? 32,768 = 1.8mhz, see figure 13. the ? rst null becomes f n = 7.04khz with an osr of 256 (an output rate of 880hz) and f o grounded. while the null has shifted, the sample rate remains constant. as a result of constant modulator sampling rate, the linearity, offset and full-scale performance remains unchanged as does the ? rst multiple of f s . figure 12. ltc2440 normal mode rejection (internal oscillator) figure 13. ltc2440 normal mode rejection (internal oscillator) differential input signal frequency (hz) 47 C140 normal mode rejection (db) C130 C120 C110 C100 51 55 59 63 2440 f12 C90 C80 49 53 57 61 differential input signal frequency (hz) 0 C60 C40 0 1440 f13 C80 C100 1000000 2000000 C120 1.8mhz C140 C20 normal mode rejection (db) rejection > 120db table 5. osr vs notch frequency (f n ) with internal oscillator running at 9mhz osr notch (f n ) 64 28.16khz 128 14.08khz 256 7.04khz 512 3.52khz 1024 1.76khz 2048 880hz 4096 440hz 8192 220hz 16384 110hz 32768* 55hz *simultaneous 50/60 rejection ltc2440 21 2440fd applications information figure 14. ltc2440 normal mode rejection (external oscillator at 90khz) the sample rate f s and null f n , my also be adjusted by driving the f o pin with an external oscillator. the sample rate is f s = f eosc / 5, where f eosc is the frequency of the clock applied to f o . combining a large osr with a reduced sample rate leads to notch frequencies f n near dc while maintaining simple antialiasing requirements. a 100khz clock applied to f o results in a null at 0.6hz plus all harmonics up to 20khz, see figure 14. this is useful in applications requiring digitalization of the dc component of a noisy input signal and eliminates the need of placing a 0.6hz ? lter in front of the adc. an external oscillator operating from 100khz to 20mhz can be implemented using the ltc1799 (resistor set sot-23 oscillator), see figure 22. by ? oating pin 4 (div) of the ltc1799, the output oscillator frequency is: f mhz k r osc set = ? ? ? ? ? ? 10 10 10 the normal mode rejection characteristic shown in fig- ure 14 is achieved by applying the output of the ltc1799 (with r set = 100k) to the f o pin on the ltc2440 with sdi tied high (osr = 32768). reduced power operation in addition to adjusting the speed/resolution of the ltc2440, the speed/resolution/power dissipation may also be adjusted using the automatic sleep mode. during the conversion cycle, the ltc2440 draws 8ma supply current independent of the programmed speed. once the conversion cycle is completed, the device automatically enters a low power sleep state drawing 8a. the device remains in this state as long as cs is high and data is not shifted out. by adjusting the duration of the sleep state (hold cs high longer) and the duration of the conversion cycle (programming osr) the dc power dissipation can be reduced, see figure 16. for example, if the osr is programmed at the fastest rate (osr = 64, t conv = 0.285ms) and the sleep state is 10ms, the effective output rate is approximately 100hz while the average supply current is reduced to 240a. by further extending the sleep state to 100ms, the effective output rate of 10hz draws on average 30a. noise, power, and speed can be optimized by adjusting the osr (noise/speed) and sleep mode duration (power). differential input signal frequency (hz) 0 C40 C20 0 8 2440 f14 C60 C80 246 10 C100 C120 C140 normal mode rejection (db) ltc2440 22 2440fd applications information ltc2440 input structure modern delta sigma converters have switched capacitor front ends that repeatedly sample the input voltage over some time period. the sampling process produces a small current pulse at the input and reference terminals as the capacitors are charged. the ltc2440 switches the input and reference to a 5pf sample capacitor at a frequency of 1.8mhz. a simpli? ed equivalent circuit is shown in figure 16. the average input and reference currents can be expressed in terms of the equivalent input resistance of the sample capacitor, where: req = 1/(f sw ? ceq) when using the internal oscillator, f sw is 1.8mhz and the equivalent resistance is approximately 110k. driving the input and reference because of the small current pulses, excessive lead length at the analog or reference input may allow re? ections or ringing to occur, affecting the conversion accuracy. the key to preserving the accuracy of the ltc2440 is complete settling of these sampling glitches at both the input and reference terminals. there are several recommended methods of doing this. figure 15. reduced power timing mode figure 16. ltc2440 input structure sleep convert sleep convert sleep 8ma 2440 f15 8a 8a 8ma 8a data out data out converter state supply current cs v ref + v in + v cc r sw (typ) 500 i leak i leak v cc i leak i leak v cc r sw (typ) 500 c eq 5pf (typ) (c eq = 3.5pf sample cap + parasitics) r sw (typ) 500 i leak i in + v in C i in C i ref + i ref C 2440 f16 i leak v cc i leak i leak switching frequency f sw = 1.8mhz internal oscillator f sw = f eosc /5 external oscillator v ref C r sw (typ) 500 ltc2440 23 2440fd applications information figure 18. input capacitors allow longer connection between the low impedance source and the adc. direct connection to low impedance sources if the adc can be located physically close to the sensor, it can be directly connected to sensors or other sources with impedances up to 350 with no other components required (see figure 17). longer connections to low impedance sources if longer lead lengths are unavoidable, adding an input capacitor close to the adc input pins will average the charging pulses and prevent re? ections or ringing (see figure 18). averaging the current pulses results in a dc input current that should be taken into account. the re- sulting 110k input impedance will result in a gain error of 0.44% for a 350 bridge (within the full scale specs of many bridges) and a very low 12.6ppm error for a 2 thermocouple connection. buffering the ltc2440 many applications will require buffering, particularly where high impedance sources are involved or where the device being measured is located some distance from the ltc2440. when buffering the ltc2440 a few simple steps should be followed. figure 19 shows a network suitable for coupling the inputs of a ltc2440 to a ltc2051 chopper-stabilized op amp. the 3v offset and low noise of the ltc2051 make it a good choice for buffering the ltc2440. many other op amps will work, with varying performance characteristics. the ltc2051 is con? gured to be able to drive the 1f ca- pacitors at the inputs of the ltc2440. the 1f capacitors should be located close to the adc input pins. the measured total unadjusted error of figure 19 is well within the speci? cations of the ltc2440 by itself. most autozero ampli? ers will degrade the overall resolution to some degree because of the extremely low input noise of the ltc2440, however the ltc2051 is a good general purpose buffer. the measured input referred noise of two ltc2051s buffering both ltc2440 inputs is approximately double that of the ltc2440 by itself, which reduces the ef- fective resolution by 1-bit for all oversample ratios. adding gain to the ltc2051 will increase gain and offset errors and will not appreciably increase the overall resolution, so it has limited bene? t. procedure for coupling any ampli? er to the ltc2440 the ltc2051 is suitable for a wide range of dc and low frequency measurement applications. if another ampli- ? er is to be selected, a general procedure for evaluating the suitability of an ampli? er for use with the ltc2440 is suggested here: 1. perform a thorough error and noise analysis on the ampli? er and gain setting components to verify that the ampli? er will perform as intended. 2. measure the large signal response of the overall circuit. the capacitive load may affect the maximum slew rate of the ampli? er. verify that the slew rate is adequate for the figure 17. direct connection to low impedance (<350) source is possible if the sensor is located close to the adc. 2440 f17 ref + ref C in + in C ltc2440 1f 4.5v to 5.5v 2440 f18 1f 4.5v to 5.5v remote thermocouple v ref + v cc gnd in + in C ltc2440 1f 1f ltc2440 24 2440fd applications information fastest expected input signal. figure 20 shows the large signal response of the circuit in figure 19. 3. measure noise performance of the complete circuit. a good technique is to build one ampli? er for each input, even if only one will be used in the end application. bias both ampli? er outputs to midscale, with the inputs tied together. verify that the noise is as expected, taking into account the bandwidth of the ltc2440 inputs for the osr being used, the ampli? ers broadband voltage noise and 1/f corner (if any) and any additional noise due to the ampli? ers current noise and source resistance. for more information on testing high linearity adcs, refer to linear technology design solutions 11. input bandwidth and frequency rejection the combined effect of the internal sinc 4 digital ? lter and the digital and analog autocalibration circuits determines the ltc2440 input bandwidth and rejection characteristics. the digital ? lters response can be adjusted by setting the oversample ratio (osr) through the spi interface or by supplying an external conversion clock to the f o pin. figure 19. buffering the ltc2440 from high impedance sources using a chopper ampli? er figure 20. large signal input settling time indicates completed settling with selected load capacitance. figure 21. dynamic input current is attenuated by load capacitance and completely settled before the next conversion sample resulting in no reduction in performance. v cc f o ref + ref C sck busy in + in C sdo cs ext 0.1 f 4 13 5 6 12 1, 8, 9, 16 11 10 15 sdi 7 5v 10f 0.01f ltc2440 2440 f19 14 10 in+ 5k c2 c2, c5 taiyo yuden jmk107bj105ma 4.7f 8-12v lt1236-5 1f c1 r1 r2 r4 r5 0.01f 1 / 2 ltc2051hv c5 1f 10 inC 5k c4 0.01f 1 / 2 ltc2051hv + C + C 2440 f20 100s/div 100mv/div 2440 f21 5ns/div 2mv/div ltc2440 25 2440fd applications information table 6 lists the properties of the ltc2440 with various combinations of oversample ratio and clock frequency. understanding these properties is the key to ? ne tuning the characteristics of the ltc2440 to the application. maximum conversion rate the maximum conversion rate is the fastest possible rate at which conversions can be performed. first notch frequency this is the ? rst notch in the sinc 4 portion of the digital ? lter and depends on the fo clock frequency and the oversample ratio. rejection at this frequency and its multiples (up to the modulator sample rate of 1.8mhz) exceeds 120db. this is 8 times the maximum conversion rate. effective noise bandwidth the ltc2440 has extremely good input noise rejection from the ? rst notch frequency all the way out to the modulator sample rate (typically 1.8mhz). effective noise bandwidth is a measure of how the adc will reject wideband input noise up to the modulator sample rate. the example on the following page shows how the noise rejection of the ltc2440 reduces the effective noise of an ampli? er driv- ing its input. table 6 oversample ratio (osr) adc noise* enob (v ref = 5v)* maximum conversion rate first notch frequency effective noise bw C3db point (hz) internal 9mhz clock external f o internal 9mhz cloc k external f o internal 9mhz clock external f o internal 9mhz clock external f o 64 23v 17 3515.6 f o /2560 28125 f o /320 3148 f o /2850 1696 f o /5310 128 3.5v 20 1757.8 f o /5120 14062.5 f o /640 1574 f o /5700 848 f o /10600 256 2v 21.3 878.9 f o /10240 7031.3 f o /1280 787 f o /11400 424 f o /21200 512 1.4v 21.8 439.5 f o /20480 3515.6 f o /2560 394 f o /22800 212 f o /42500 1024 1v 22.4 219.7 f o /40960 1757.8 f o /5120 197 f o /45700 106 f o /84900 2048 750nv 22.9 109.9 f o /81920 878.9 f o /1020 98.4 f o /91400 53 f o /170000 4096 510nv 23.4 54.9 f o /163840 439.5 f o /2050 49.2 f o /183000 26.5 f o /340000 8192 375nv 24 27.5 f o /327680 219.7 f o /4100 24.6 f o /366000 13.2 f o /679000 16384 250nv 24.4 13.7 f o /655360 109.9 f o /8190 12.4 f o /731000 6.6 f o /1358000 32768 200nv 24.6 6.9 f o /1310720 54.9 f o /16380 6.2 f o /1463000 3.3 f o /2717000 *adc noise increases by approximately 2 when osr is decreased by a factor of 2 for osr 32768 to osr 256. the adc noise at osr 128 and osr 64 include effects from internal modulator quantization noise. ltc2440 26 2440fd example: if an ampli? er (e.g. lt1219) driving the input of an ltc2440 has wideband noise of 33nv/ hz, band-limited to 1.8mhz, the total noise entering the adc input is: 33nv/ hz ? 1.8mhz = 44.3v. when the adc digitizes the input, its digital ? lter ? lters out the wideband noise from the input signal. the noise reduction depends on the oversample ratio which de? nes the effective bandwidth of the digital ? lter. at an oversample of 256, the noise bandwidth of the adc is 787hz which reduces the total ampli? er noise to: 33nv/ hz ? 787hz = 0.93v. the total noise is the rms sum of this noise with the 2v noise of the adc at osr=256. 0.93/v 2 + 2v 2 = 2.2v. increasing the oversampling ratio to 32768 reduces the noise bandwidth of the adc to 6.2hz which reduces the total ampli? er noise to: 33nv/ hz ? 6.2hz = 82nv. the total noise is the rms sum of this noise with the 200nv noise of the adc at osr = 32768. 82nv 2 + 2v 2 = 216nv. in this way, the digital ? lter with its variable oversampling ratio can greatly reduce the effects of external noise sources. using non-autozeroed ampli? ers for lowest noise applications ultralow noise applications may require the use of low noise bipolar ampli? ers that are not autozeroed. because the ltc2440 has such exceptionally low offset, offset drift and 1/f noise, the offset drift and 1/f noise in the ampli- ? ers may need to be compensated for to retain the system performance of which the adc is capable. the circuit of figure 23 uses low noise bipolar ampli? ers and correlated double sampling to achieve a resolution of 14nv, or 19 effective bits over a 10mv span. each measure- ment is the difference between two adc readings taken with opposite polarity bridge excitation. this cancels 1/f noise below 3.4hz and eliminates errors due to parasitic thermocouples. allow 750s settling time after switching excitation polarity. applications information ltc2440 27 2440fd information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description typical applications figure 22. simple external clock source gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0204 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .0532 ?.0688 (1.35 ?1.75) .008 ?.012 (0.203 ?0.305) typ .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale v cc f o ref + ref C sck busy in + in C sdo gnd cs ext 2 14 3 4 51 2 3 0.1 f r set 4 nc 50 13 5 6 12 1, 8, 9, 16 11 10 15 sdi 7 v cc reference voltage 0.1v to v cc analog input range C0.5v ref to 0.5v ref 1f 4.5v to 5.5v ltc2440 v + gnd out div set 2440 ta05 ltc1799 3-wire spi interface ltc2440 28 2440fd linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2002 lt 1008 rev d ? printed in usa related parts typical application part number description comments lt1025 micropower thermocouple cold junction compensator 80a supply current, 0.5c initial accuracy ltc1043 dual precision instrumentation switched capacitor building block precise charge, balanced switching, low power ltc1050 precision chopper stabilized op amp no external components 5v offset, 1.6v p-p noise lt1236a-5 precision bandgap reference, 5v 0.05% max, 5ppm/c drift lt1461 micropower series reference, 2.5v 0.04% max, 3ppm/c max drift ltc1592 ultraprecise 16-bit softspan tm dac six programmable output ranges ltc1655 16-bit rail-to-rail micropower dac 1lsb dnl, 600a, internal reference, so-8 ltc1799 resistor set sot-23 oscillator single resistor frequency set ltc2053 rail-to-rail instrumentation ampli? er 10v offset with 50nv/c drift, 2.5v p-p noise 0.01hz to 10hz ltc2400 24-bit, no latency ? adc in so-8 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2401/ltc2402 1-/2-channel, 24-bit, no latency ? adc in msop 0.6ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2404/ltc2408 4-/8-channel, 24-bit, no latency ? adc 0.3ppm noise, 4ppm inl, 10ppm total unadjusted error, 200a ltc2410/ltc2413 24-bit, no latency ? adc 800nv rms noise, 5ppm inl/simultaneous 50hz/60hz rejection ltc2411 24-bit, no latency ? adc in msop 1.45v rms noise, 6ppm inl ltc2420ltc2424/ ltc2428 1-/4-/8-channel, 20-bit, no latency ? adcs 1.2ppm noise, 8ppm inl, pin compatible with ltc2400/ ltc2404/ltc2408 softspan is a trademark of linear technology corporation. figure 23. bridge reversal eliminates 1/f noise and offset drift of a low noise, non-autozeroed, bipolar ampli? er. circuit gives 14nv noise level or 19 effective bits over a 10mv span ref + ref C in + in C v ref 0.1f 10f 4 ltc2440 2440 f22 +7v lt1461-5 1k 0.1% 10 100 0.1% 0.047 f 1f 1k 0.1% 10 0.047 f 1f + C C + 2x lt1677 2x siliconix si9801 5,6,7,8 100k 100k top_n top_p v ref 1 3 2 5,6,7,8 4 100k 100k bottom_n bottom_p v ref 1 3 2 4 |
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